The bottleneck for a pipelined microprocessor architecture is the high access time of the memory system. Classical approaches to solve this problem use large caches and transmit multiple data words per clock after an initial high memory access time. Small microcontroller designs are limited in the amount of cache that can be on chip and they cannot support the large sizes of high latency but high throughput narrow memory. Thus, a need for a configurable cache for a microcontroller or microprocessor exists.